1. Field of the Invention
The present invention relates to a register controlling apparatus, and in particular, to an improved register controlling apparatus which is capable of processing a C programming language instructions efficiently and at a high speed in a central processing unit (hereinafter, called CPU) by controlling a plurality of registers.
2. Description of the Prior Art
Conventionally, a register is a semiconductor memory device which is accessed by a CPU and employed in the writing and reading of data and various kinds of operations.
In the case of a reduced instruction set computer (RISC)-type CPU, there are provided tens of or hundreds of registers, and the construction of all the registers is divided into 2-16 banks.
As shown in FIG. 1, the conventional register controlling apparatus includes a CPU 1 for outputting a register address (Raddr) in accordance with control data input through a data or reading written data bus, and a memory 2 for writing data in a corresponding domain in accordance with the register address (Raddr) output from the CPU.
The register addresses are sequential from the first to the last with consecutive numbers, and each address corresponds to a respective register.
Referring to the accompanying drawings, the operation of the conventional register controlling apparatus will now be described in detail.
First, when an arbitrary program routine is set by the user, the CPU 1 receives control data through the data bus and then outputs a register address (Raddr). The memory 2 selects each corresponding address in accordance with the register address (Raddr) and runs the set routine.
Each register has a consecutive address, and when there are one hundred registers, the register addresses include Raddr0-Raddr99.
When the user enters a subroutine from an arbitrary program routine to run a more efficient high-level language, such as a C programming language, he or she should know how to use a new routine in the subroutine.
When the user is using n registers in an arbitrary routine and wants to call a subroutine to use m registers, to implement the subroutine, he or she should know which register he or she used in the high order routine and which register he or she can use in the present routine.
That is, when the user is using 11 registers (R0-R10) in the high order routine and wants to call a subroutine to use seven registers, he or she can use registers R11-R17.
The above-described operation would be programmed as follows:
That is, when allocating the programs, as shown above, the subroutine B should know in advance that registers R0-R10 will be used in the routine A due to the characteristic that a register having a specific address is used only in a specific routine.
Therefore, when a register is to be used in each routine through some program, as shown in FIG. 3, the CPU 1 accesses a register allocated in each routine (A, B, C, . . . , N) in accordance with the flow of the program.
However, in the above-described procedure, it is very difficult to create a program because a register domain used by each routine should be set in advance when creating a program, and a register having a specific address has a low usage efficiency since the register having the specific address can use only the specific address.
Further, since the above-mentioned program is not proper for a high level language, especially for a C programming language, a low level language such as an assembly language should be disadvantageously used.
In addition, although, a program managing a register (or a memory) may be added when compiling a program to prevent the above-described problem, the size of the program is enlarged and the running speed is undesirably slowed down.
FIG. 2 is another embodiment of the conventional register controlling apparatus, wherein to solve the above-described problem, a higher performance RISC type CPU is substituted for the CPU 1 in FIG. 1, and the entire register range is divided into N register banks (4-1, 4-2, . . . , 4-n) to be used as the memory 2.
Here, the RISC type CPU 3 has tens or hundreds of registers. That is, the entire register range is divided into 2-16 banks and each bank includes eight or sixteen registers.
This conventional register controlling apparatus will now be described in detail.
First, when the user runs a program and performs an arbitrary routine, the RISC type CPU 3 selects one register bank in a register stack divided into the N register banks 4-1, 4-2, . . . , 4-n. Then by using a register allocated in the selected register bank, the present routine is run.
When the user calls a subroutine from the present routine which is a high order routine, the called subroutine automatically selects the next register bank in the register stack divided into the N register bank 4-1, 4-2, . . . , 4-n to run the program and then returns to the high order routine when the running of the program is done.
When the subroutine returns to the high order routine, since the register bank which the subroutine selected and used is automatically released, the register bank can be reused when the subroutine is called from the high order routine next time.
That is, as shown in FIG. 4, when a subroutine B is called while using the register Bank04-1 in a high order routine A, the called subroutine B uses the next register Bank14-2, and then returns to the high order routine A and the selection of the register Bank14-2 is released.
Then, when a subroutine C is called from the high order routine A, the called subroutine C can also use the register Bank14-2 used in the subroutine B, and when a subroutine D is called from the subroutine C, the called subroutine D can use a next register Bank24-3.
When the selected register Bank24-3 returns to the high order routine C from the subroutine D, the selection of the register Bank24-3 is released. Therefore, when a subroutine E is called from the subroutine C, the called subroutine E can use the register Bank24-3 used in the previous subroutine C.
Therefore, in this conventional register controlling apparatus, when a subroutine is called from a high order routine to run a program and returns to the high order routine, since the register bank used in the previous subroutine can be used in another subroutine, the register controlling apparatus can achieve improved application efficiency of the register, while remaining suitable for the processing of the program created in the C programming language.
However, in another embodiment of the conventional register controlling apparatus, since the entire register complement is divided into a predetermined number of register banks, registers are sometimes lacking or overabundant depending on the run routine, resulting in the undesirable lowering of the application efficiency of the register.
That is, in some specific subroutines so few registers are used that many unused registers remain, while in other subroutines, subroutines are called continuously enough to exceed the number of register banks primarily because, the registers of one bank that service one routine can not be used in servicing another register even if they are not being used, resulting in the lack of available registers.
In addition, when a parameter between each routine in a C programming language is set to be an address of an arbitrary variable, a variable of one routine is difficult to access from another routine.
Accordingly, it is an object of the present invention to provide an improved register controlling apparatus which is capable of setting the number of registers used by each routine suitably depending on each routine, and of processing the calling of subroutines until all the registers are used when each routine uses a small number of registers.
It is another object of the present invention to provide an improved register controller which is capable of setting an available register domain by selectively adding up the values of a register logical address and a local register pointer from CPU and the value of a local register counter and of performing the continuous calling of another subroutine from a higher order routine by releasing the set register available domain when a subroutine returns to a higher order routine.
To achieve the above object, there is provided an enhanced register controlling apparatus which includes a CPU for outputting the values of the register logical address, a first control signal and local register pointer, and the number (count value) of available registers, a register controller for selectively adding the values of a register logical address and a local register pointer, and the number (count value) of available registers and outputting a register physical address, and a memory for writing data in a domain set by the register physical address of the register controller or reading the written data.
To achieve another object of the present invention, there is provided a semiconductor apparatus in which a register controller controls the creation and access operation of a register physical address for the storing domain of a memory, wherein the register controller include a control circuit for outputting first and second control signals, respectively, in accordance with the control of a CPU, a local register pointer for setting a start address of register domains which will be used in a presently running program routine, a local register counter for setting the number of registers which will be used in the present/y running program routine, and an adder for adding the register logical addresses outputted from the CPU in accordance with the first control signal from the control circuit and the values of the local register pointer and then outputting a register physical address.